The MADNESS project aims at the definition of innovative system-level design methodologies for MPSoC embedded systems, extending the classic concept of design space exploration to cope with high heterogeneity, technology scaling, system reliability and multi-application domains.

Keywords: system-level design, design space exploration, technology awareness, heterogeneity, fault tolerance, adaptivity

Main Objectives

The proposed methodologies will extend the classic concept of design space exploration to:

• Improve design predictability, bridging the so called "implementation gap", i.e. the gap between the results that can be predicted during the system-level design phase and those eventually obtained after the on-silicon implementation.
• Consider, in addition to traditional metrics (such as cost, performance and power consumption), continued availability of service, taking into account fault resilience as one of the optimization factors to be satisfied.
• Support adaptive runtime management of the architecture, considering, while tailoring the architecture, new metrics posed by novel dynamic strategies and advanced support for communication issues that will be defined.

Technical Approach

The project proposes an extended system-level design space exploration approach. The DSE is seen as an iterative process operating on a library of heterogeneous IP cores, exposing a large number of degrees of freedom, as typical for industrial-strength components.

In order to improve the design predictability, the project will introduce a specific layer for rapid and accurate emulation, to be exploited for architectural evaluation inside the DSE process. In detail, it will allow to take into account, during system-level decision phase, the impact of the variables related with a prospective physical implementation of the architecture (e.g. wiring capacitances and delay, 2D floorplanning). Moreover, this layer will provide the capability of performing, when needed during the optimization process, a detailed estimation of the performance and the power consumption of a candidate architecture, relying on an FPGA-based environment for on-hardware prototyping. The power consumption evaluation will be obtained annotating the FPGA emulation results with energy values estimated in a “technology-aware” manner.

Novel design methodologies for fault tolerance and for adaptive runtime management will be proposed. These methodologies will act at different levels of abstraction and on different phases of the design flow. Their introduction will influence the system-level design algorithm, since it will require new metrics to be taken into account by the optimization process. Besides that, it will require the development of new dedicated hardware support and, thus, new IPs are likely to be developed.

Key Issues

Modern embedded systems usually integrate components provided by different parties, very often yielding a high level of design complexity to be handled by the designer. Different computational tasks to be executed often offer different kinds and degrees of parallelism, thus optimally fitting to a specific kind of processing elements.

In order to improve the overall productivity, an effective system-level design should be handled in a novel manner, taking into account, at its early stages, a bigger number of variables as well as more complex IP cores inside the design space available to the designer. Moreover, the efficient “static approach” to the design of embedded processors needs to be extended to MPSoC design, and in certain cases needs to include dynamic behaviour. This is particularly the case when multiple applications are executed at the same time, unpredictably interfering with each other at runtime and posing the need for the assurance of a given level of Quality of Service. In addition, given the increasing complexity of the systems, a certain degree of fault tolerance must be guaranteed, but constraints presented by embedded systems design make approaches involving massive redundancy hardly adoptable. Both these issues require the support inside modern MPSoCs of a certain degree of adaptivity.

To take meaningful system-level decisions, moreover, the designer must deal with several problems related to modern technology nodes and rely on accurate estimations of the hardware costs of each candidate architectural solution.

Expected Impact

The MADNESS project will deliver advanced technology and specific tools for strengthening European excellence in the design of multi-processor heterogeneous embedded systems. Here is a brief list of the expected impacts targeted by the MADNESS project.

• Significantly increased productivity of embedded system development.
• Improved competitiveness of European companies that rely on the design and integration of embedded systems in their products by reducing design costs and time to market.
• Emergence and growth of new companies that supply design tools and associated software.
• Stimulated high-tech European companies, in particular SMEs, which offer innovative products and services for embedded systems design.
• Reinforced European scientific and technological leadership in the design of complex embedded systems.

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